80 Seties

81C55 - 2k CMOS Statis RAM with I/O Ports and Timer

Photograph

Features 256 words x 8bits RAM Single Power Supply, 3 to 6V Completely Static Operation On-chip address latch 8-bit programmable I/O ports TTL Compatible RAM data hold characteristic at 2V 6-bit programmable I/O port 14-bit programmable binary counter/timer Multiplexed address / data bus Direct interface with 80C85

Pin Description Pin Number Description 1 PC3 - Port C 2 PC4 - Port C 3 TIMER IN - Timer Input 4 RESET - Reset 5 PC5 - Port C 6 TIMER OUT - Timer Output (Active Low) 7 IO/M - Internal Memory Select 8 CE - Chip Enable (Active Low) 9 RD - Read (Active Low) 10 WR - Write (Active Low) 11 ALE - Address Latch Enable 12-19 AD0-AD7 - Address Data Bus 20 GND - Ground 21-28 PA0-PA7 - Port A 29-36 PB0-PB7 - Port B 37-39 PC0-PC2 - Port C 40 Vcc - +5V Positive Supply

Pin Layout Dimensional Drawing

Technical Data Data Sheet Data Sheet for 81C55 Application Notes