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AD7730 CMOS, 24-Bit Sigma-Delta, Bridge Transducer ADC Datasheet
Photograph
Features
- Resolution of 230,000 Counts (Peak-to-Peak)
- Offset Drift: 5nV/°C
- Gain Drift: 2ppm/°C
- Line Frequency Rejection: >150dB
- Buffered Differential Inputs
- Programmable Filter Cutoffs
- Specified for Drift Over Time
- Operates with Reference Voltages of 1V to 5V
Pin Layout
Pin Description
| Pin Number | Description |
|---|---|
| 1 | SCLK - Serial Clock |
| 2 | MCLK IN - Master Clock In |
| 3 | MCLK OUT - Master Clock Out |
| 4 | POL - Clock Polarity |
| 5 | SYNC - Synchronization (Active Low) |
| 6 | RESET - Chip Reset (Active Low) |
| 7 | Vbias - Analog Output |
| 8 | AGND - Analog Ground |
| 9 | AVdd - Analog Positive Supply |
| 10 | AIN1+ - Analog Input Channel 1 |
| 11 | AIN1- - Analog Input Channel 1 |
| 12 | AIN2+ - Analog Input Channel 2 |
| 13 | AIN2- - Analog Input Channel 2 |
| 14 | REF IN+ - Reference Input |
| 15 | REF IN- - Reference Input |
| 16 | ACX - See Datasheet |
| 17 | ACX - See Datasheet (Active Low) |
| 18 | STANDBY - Standby Mode (Active Low) |
| 19 | CS - Chip Select (Active Low) |
| 20 | RDY - Ready Signal (Active Low) |
| 21 | DOUT - Serial Data Output |
| 22 | DIN - Serial Data Input |
| 23 | DVdd - Digital Positive Supply |
| 24 | DGND - Digital Ground |
Dimensional Drawing
Technical Data
